The patents U.S. Pat. No. 7,816,653, U.S. Pat. No. 8,148,760, and U.S. Pat. No. 8,288,837, which are incorporated herein by reference, disclose a semiconductor radiation detector having a so-called Modified Internal Gate (MIG). The MIG is an internal part of the semiconductor radiation detection, in which radiation-induced signal charges are collected so that the resulting net electric charge in the MIG causes measurable effects in the electric characteristics of pixels above it. Examples of such effects are changes in the current-carrying capability of the channel or base of a pixel-specific transistor. A barrier layer separates the MIG from said pixels. It constitutes, when appropriately biased, a potential energy barrier that keeps the accumulated signal charges in the MIG layer from mixing with charge carriers in the pixels, such as the charge carriers the flow of which constitutes the electric current through said channel or base. Additional information is also disclosed at the internet pages www.pixpolar.com/technology and www.pixpolar.com/blog as well as at several discussions on the blog www.image-sensors-world.blogspot.com.
In semiconductor radiation detectors the radiation induces electron hole pairs which are separated by an electric field. The charge type of the electron hole pair that is measured is referred to as signal charge and the opposite charge type is referred to as secondary charge.
The MIG detectors comprising typically a matrix of MIG pixels have several benefits over traditional radiation detectors like Complementary Metal Oxide Semiconductor (CMOS) image sensors. First of all, in the MIG pixel the interface generated charges do not mix with signal charges. Second, a buried channel having a large potential difference between the bottom of the channel and the interface can be utilized enabling considerable reduction in 1/f noise. Such a low 1/f noise buried channel results in much lower read noise. Third, Back-Side Illuminated (BSI) MIG pixels having 100% fill-factor can be easily designed. Fourth, it is easy to design fully depleted MIG pixels avoiding the diffusion of signal charges which enables very low cross-talk between pixels. Fifth, the MIG pixels comprise inherently a vertical anti-blooming mechanism meaning that blooming is not an issue. Sixth, thick fully depleted MIG pixels enable very good quantum efficiency for red and Near Infra-Red (NIR) light while cross-talk is kept at minimum level. Seventh, the signal charges are well aligned with the lowest channel threshold of the above lying readout transistor. Eighth, the MIG pixels enable linear current mode readout.
The ninth advantage is that the MIG pixels are very much compatible with analog CMOS processes. The reason for this is that leakage through the gate oxide is not an issue since the signal charge is not brought to the external gate. Another reason is that a pinned photo-diode is not required like in traditional CMOS image sensors. The pinned photo-diode is difficult to design and it is actually an adaptation from Charge Coupled Devices (CCD) and it is not inherently present in a standard CMOS process. Also the interface quality is not an issue as it is in traditional CMOS image sensors. The outcome of these facts is that one has to develop a separate CMOS image sensor process for the production of traditional CMOS image sensors whereas an existing standard analog CMOS process can be used for the production of MIG image sensors.
FIG. 1 illustrates a schematic cross-section of a typical CMOS transistor comprising a semiconductor substrate 100 of first or second conductivity type, and on the front side of the device a Shallow-Trench Isolation (STI) 130, gate 181, oxide layer (or more generally a layer of electrically insulating material) 171 surrounding the gate, and a well doping 105 of first conductivity type. In addition the CMOS transistor comprises on the front surface a source doping 111, a drain doping 112, a source contact doping 121, and a drain contact doping 122, which are all of second conductivity type.
Doped regions are physical entities, while the term pixel is more like a functional element, which means that—at least literally taken—pixels only appear in a semiconductor radiation detector when the power is on. Although separate contact dopings like the ones illustrated in FIG. 1 as 121 and 122 are often used, they are not essential. It is possible to create a pixel-specific field-effect transistor in a CMOS process so that the source and drain dopings appear as such, without separate contact dopings. In this description we use the general designation pixel dopings to mean doped regions to which an external voltage and/or current can be directly coupled to create a pixel of the semiconductor radiation detector. Thus in a structure like that in FIG. 1 the pixel dopings are the source contact doping 121 and the drain contact doping 122. In a structure without separate contact dopings the term pixel dopings would refer to the source and drain dopings.
The first and second conductivity types correspond to n and p type or vice versa. In addition, in FIG. 1 also is depicted another CMOS transistor of the same conductivity type having source 113, drain 114, source contact doping 123, drain contact doping 124, and gate 182. Also part of the source contact doping 127 and drain contact doping 128 of two neighboring pixels are depicted in FIG. 1.
FIG. 4 illustrates the schematic front side layout of a CMOS transistor wherein a cross-section along the line 493 corresponds to the cross-section presented in FIG. 1. The first type contact doping 405 is a contact doping to the first type well doping 105. The buried channel MIG pixel is formed by providing underneath the gate of a CMOS transistor a layered structure. The well doping 105 prevents the proper formation of the layered structure underneath the external gates of the transistors in FIG. 1 due to the fact that the dopant concentration of the well doping is typically much higher than the optimal dopant concentration of the layered structure. Thus an opening in the well doping 105 must be provided underneath the external gate 181.
FIG. 5 illustrates a schematic front side layout of a most basic buried channel MIG pixel manufactured with a CMOS process. The opening in the well doping 594 located partly underneath the gate area is depicted by a dashed line. The cross-section along the line 593 is presented in FIG. 2, wherein the well doping 205 comprises openings underneath the external gates 181 and 182. In the opening the MIG layer 241 acts as an internal gate collecting the signal charges which modulate the current running in the buried channel 261 of the above lying readout transistor. The barrier layer 251 acts as a barrier in between the MIG layer and the buried channel. In FIG. 2 there is also depicted the MIG layer 242, the barrier layer 252, and the buried channel layer 262 of the neighboring pixel. On the back-side of the device there is also an optional conductive back-side layer 200 of the first conductivity type which may be or may not be biased. In operation a reverse bias is applied between the source/drain contact dopings and the well doping and/or the conductive back-side layer.
The buried channel 261, 262 is not mandatory requirement for a MIG detector. A low 1/f noise buried channel offers, however, a considerable benefit for the MIG detector/pixel since it enables a significant reduction in the read noise and involves advantages in manufacturing. The latter fact is because the interface quality is of lesser importance due to the large potential difference between the interface and the channel. Thus a buried channel is an advantageous choice. A very important matter from noise point of view is also that when the pixel is reset one should be able to remove all the signal charges from the MIG layer 241, i.e., after reset the MIG layer should be fully depleted. During readout at the location where the signal charges are stored in the MIG layer the barrier layer should be fully depleted. If this is not the case the signal charges cannot properly modulate the threshold voltage of the channel and/or the current running in the channel meaning that the readout is disabled or at least inaccurate.
The arrangement of the opening 594 in the well doping 205 has been considered as the only reasonable choice for the following self-evident reasons. The fact that the STI and the contact doping are surrounded by the well doping means that the layered structure 241, 251, and 261 can be made thinner, which facilitates the coupling of the signal charges to the channel as well as the scaling of the pixel to smaller pixel sizes. In order to enable further thinning of the layered structure one could think that by arranging the opening of the well doping along the dashed line 295 the layered structure could be made even thinner because the source 213 and drain 214 dopings would be completely surrounded by the well doping 205. From the operation point of view this is, however, not recommendable since the highest threshold voltage or the highest channel resistance would be in the areas of the dashed ellipses 293 and 294 wherein the signal charge of MIG layer would have only very little effect due to the screening of the well doping.
For the above presented reasons the way to construct the opening in the well doping that has been considered the best—or even only—alternative is as depicted in FIGS. 2 and 5. The problem with this arrangement is, however, that in order to create reasonable barrier between the source 111/drain 112 dopings and the MIG layer 241 the barrier layer 251 has to be substantially deeper than the source and drain dopings as is depicted at the locations of the dashed ellipses 291 and 292 in FIG. 2. In other words, one has to take care that the source and drain dopings are not ‘eating’ too much away of the barrier layer, by utilizing a deep enough layered structure. The fact, however, that the source and drain dopings are relatively heavily doped means that they will also diffuse relatively deep down due to subsequent heat treatments, which again necessitates the use of a relatively deep layered structure which hinders pixel scaling.
In case the external gate 181 of a single MIG pixel has to support three different voltage stages (readout, integration, and reset) the amount of signal charge that can be stored in the MIG layer can be very limited. One easy solution to this problem is that one can add a selection transistor to the source. In this manner one needs to utilize only two different voltages on the external gate 181, namely readout and reset. This improves the storing capacity, also known as the Full Well Capacity (FWC) of the MIG layer.
Another way to improve the FWC as well as the cross-talk is presented in FIG. 3 illustrating more advanced MIG pixels manufactured with a non-standard CMOS process wherein deep trenches isolate each pixel including the substrate 301, 302, 303, and 304. The trenches of FIG. 3 comprise optional pixel-specific walls of electrically insulating material 335, 336, 337, and 338, next to which are optional pixel-specific walls of material 395, 396, 397, and 398 that is beneficially conductive, opaque, and a good reflector. In between the latter walls there is a trench fill 330 which is common to all of the pixels. The fact that the well dopings 305, 306, 307, and 308 in each pixel are isolated means that the reset can be aided by increasing the reverse bias between the well doping and the source/drain dopings. It would actually be enough to separate only rows of pixels with the trenches, but if pixel-specific reset were utilized each pixel would need to be separated by a trench as is depicted in FIG. 3. In case the walls 395, 396, 397, and 398 are conductive, the pixel reset can be still improved by utilizing a simultaneous reset pulse both to the walls 395, 396, 397, and 398 and to the well dopings 305, 306, 307, and 308. In other words, a reset pulse may be simultaneously coupled to the wall 396 and to the corresponding well doping 306, in case a reset will be performed to the pixel comprising the gate 182.
In case e.g. the semiconductor material is silicon, the electrically insulating material 335, 336, 337, and 338 is silicon dioxide, and the first conductivity type is n type and the second conductivity type is p type then it is beneficial to contact the walls 395, 396, 397, and 398 to the respective well dopings 305, 306, 307, and 308. In this manner no bias is required between the walls 395, 396, 397, and 398 and the well dopings 305, 306, 307, and 308 in order to form an accumulation or inversion layer of electrons at the interface between the substrate 301, 302, 303, and 304 and isolator walls 335, 336, 337, and 338. The reason for this is that the positive oxide charge in silicon dioxide is enough to create the accumulation or inversion layer of electrons. The benefit of the accumulation or inversion layer is that at the interfaces of the deep trenches protruding through the well dopings 305, 306, 307, and 308 it inhibits the formation of leakage current which would otherwise mix with the signal charges in the MIG layer (in the pixel of FIG. 2 the trenches do not protrude through the neutral well doping and thus the leakage at the interface of the trench is not an issue, i.e., the interface leakage is collected by source and drain).
In case the substrate material is silicon, the first conductivity type is n type, and the back-side layer 300 is formed of silicon dioxide an accumulation or inversion layer of electrons forms also at the back-side interface between the back-side layer 300 and the substrate 301, 302, 303, and 304 due to the positive oxide charge present in silicon dioxide. The great advantage of the arrangement is that the back-side silicon dioxide layer forms spontaneously on the back-side meaning that after the back-side thinning neither back-side implantation nor back-side laser annealing is required which simplifies processing and reduces back-side originated dark current. One should note, however, that even if the back-side layer 300 is formed spontaneously of silicon dioxide and only a simple trench 330 is used without the additional walls 335, 336, 337, and 338 as well as 395, 396, 397, and 398, the processing is still a demanding task due to the fact that high aspect ratio trenches are required since otherwise the fill-factor would be compromised. Another issue is naturally also that such a process would not be a standard CMOS process.
In the above listed patents (U.S. Pat. No. 7,816,653, U.S. Pat. No. 8,148,760, and U.S. Pat. No. 8,288,837 which are incorporated as reference) different types of reset structures have also been present which enable larger FWC. The problem with these reset structures has been, however, that they typically reduce the fill-factor.
Further, a publication WO 2007/077286 discloses a semiconductor radiation detector for detecting visible light. The semiconductor radiation detector comprises a structure wherein a first contact of a first conductivity type is adapted to collect secondary charges from a bulk layer being of first conductivity type material.
Document U.S. 2009/001435, in turn, discloses a semiconductor radiation detector device, which comprises means for reading signal charge from a modified internal gate layer using a floating gate configuration, in which a gate of a readout transistor floats in respect of said pixel voltage.